Company Name: Google India

Company Website:

Job Post: ASIC physical verification & convergence engineer

Experience: Entry-level Engineer
Job Location: Bangalore
Job Description:
Our computational challenges are so big, complex, and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As an ASIC Physical Verification and Convergence Engineer, you will develop high-performance hardware to enable Google’s continuous innovations and work with Application-Specific Integrated Circuits (ASIC).

You will be responsible for driving the overall physical convergence for high-performance designs, including setting up the physical analysis flows and methodology to achieve a clean by construction design, and working with the implementation engineers for a timely physical convergence.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology
Qualification Required:
  • Bachelor’s degree in Electrical Engineering or related field, or equivalent practical experience.
  • Experience with different physical verification checks like DRC, LVS, Antenna, ERC, PERC, ESD, etc.
  • Experience in sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV.
  • Experience in PnR tools like ICC/Innovus with regards to physical convergence.
Preferred qualifications:
  • Tape out experience in cutting-edge technology nodes.
  • Experience with static timing analysis and signoff convergence.
  • Understanding of high-performance synthesis and PnR optimizations.
  • Basic device physics skills.
  • Drive the overall sign-off physical convergence for high-performance designs.
  • Define the overall physical convergence methodology, plan out the timeline, and work closely with the block owners to achieve physical convergence through systematic fixes and minimal manual effort.

How to apply: Click here


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